J. Kissel, D. Sigg, D. Barker
ECR E2100485
WP 12901

Continuing on the deprecation of 18-bit DAC path (ECR E2100485), we upgraded the h1iscex's DAC0 card yesterday from an 18- to a 20-bit DAC (LHO:88333). One of the front-end models that use that DAC is the h1calex model.

In this aLOG, I discuss the front-end model changes we implemented to support this change.

I show the differences in before vs. after in the following screenshots. All changes were made at the top level of the model, no library parts were changed.
    - Top level model BEFORE vs. AFTER.
        Functional Changes:
        :: Changed the CDS part representation of the DAC from a 18- to 20-bit DAC.
        :: Added a constant of 4.0 ***, whose output is piped into a goto tag, CAL_FACTOR.
        :: The CAL_FACTOR from tag is first piped into a EPICs read back for display on MEDM (and for recording in frames), which will manifest as the channel H1:CAL-EX_DAC_CAL_FACTOR
        :: Then CAL_FACTOR is piped into multiplication blocks downstream of the DAC outputs such that the two channels used by the model CH5 and CH6 (with the count starting at 0; CH6 and CH7 in the analog world where counting starts at 1)

        Aesthetic Changes:
        :: Added the modern labels for direct IO chassis and inter-(computer)-process communication
        :: Detached the RFM IPC that ships the PCAL excitations to the corner station from its direct wire pick-off and "changed" it's input to be the tag that already exists to ship the signal to the DAC
        :: Moved that IPC system down to the left under the "new" RFM section, which allows for the model to conform to modern convention of having clear/clean separate sections for "input" "controls" and "output."
        :: Changed the color of the CDS parameters block to be orange, as is standard.

     - Another view of the top level to better highlight which signals are multiplied by four, and where in the signal change BEFORE vs. AFTER

The h1calex model has been committed, and rev-updated to to 
    /opt/rtcds/userapps/release/cal/h1/models/
        h1calex.mdl         r23189 --> r34056


*** Because this model houses both the PCAL system, Hardware Injection and the DuoTone system -- critical flywheels for the detector calibration, we decided to implement our usual gain scaling of (exactly) 4.0x to compensate for the change in calibration (from 20/2^18 to 20/2^20 [ Vpp_differential / ct]) the DAC card upgrade as a hard-coded constant in the front-end, rather than in an "adjustable/changeable" filter module in a filter bank just upstream of the DAC output.

Wed Dec 03 10:09:57 2025 INFO: Fill completed in 9min 54secs

Gerardo confirmed a good fill curbside. Plot looks strange because temps were starting positive.

WP12901 Daniel, Marc, Fil, Jonathan, Richard, Jeff, Oli, EJ, Dave:

Following from Monday's success in upgrading h1susey to the new LIGO-DACs on Tuesday 02dec2025 we upgraded h1susex to use LIGO-DACs.

This was a slightly different upgrade compared to h1susey because for the past 18 months h1susex ESDs have been driven using an early version of the LIGO-DAC. The h1susetmx model was using the GenStd 18/20-bit DACs for the upper stages and the LIGO-DAC for the L3 and ESD. The other models (h1sustmsx and h1susetmxpi) continued to use the Gen Std DACs.

The ESD and PI drives were being driven by a single 20bit-DAC using the special PI-AI chassis (first 6 chans through standard filters and output via DB15, last 2 chans through PI filters and output via DB9). When we upgraded the ESD drives to the LIGO-DAC we retained the original PI-AI chassis for these signals and temporarily installed the spare PI-AI chassis for h1susetmxpi 20bit-DAC's exclusive use.

The original LIGO-DAC used the 8-channel interface card. This card took the 32 channels from the LIGO-DAC and outputed the first 8 using its onboard DB25 connector. The remaining 24 channels were distributed using 3 Header Slot Plates (each with a DB25) ribbon cabled to the interface card. To fit these into the chassis, we displaced the two BIO cards to A4-3 and A4-4. 

The IO Chassis changes were then:

Remove first-gen LIGO-DAC card, its 8chan interface card and the 3 header slot plates.

Remove the 3 18bit-DACs and their interface cards

Remove the 2 20-bit DACs and their interface cards

Install 2 LIGO-DACs in A1-4 and A2-2 with their new LIGO-DAC interface cards

Move the 2 BIO cards back to A4-1 and A4-2.

Fil upgraded all the AI chassis for LIGO-DAC SCSI Connection, duplicating what was done at EY. The second LIGO-DAC drives the PI-AI chassis, the first LIGO-DAC drives the 2 standard AI chassis, now daisy chained together.

Temporary cabling from the original LIGO-DAC chans 16-31 looped over to h1iscex were removed.

LIGO-DACs ADDED

Cards Removed

* 20bit-DAC installed into h1iscex, now suspect.

WP12901. Daniel, Jeff, Oli, Fil, Marc, Jonathan, EJ, Tony, Dave:

Summary:

Yesterday I replaced h1iscex's 18bit-DAC with a 20bit-DAC as part of the project to eliminate all 18bit-DACs from production. There is currently no indication that the 20bit-DAC is driving the AI chassis with any voltage, investigation is ongoing.

Details:

The 18/20 bit DACs use the same interface card, so for the upgrade I was able to pull the IO Chassis out half way with cables still attached to access the PCIe bus. I removed the old 18bit-DAC and replaced it with on of the 20bit-DACs from h1susex upgrade

I do not know if the 20bit-DAC from h1susex was the one driving the PI or the one which had been idle since the LIGO-DAC went in mid 2024.

The original interface card and ribbon cable were reused. No field cabling was disconnected, no AI chassis were powered down.

Upgrade was done between 12:00 and 13:00 Tue 02dec2025.

Later that afternoon Tony found that the PCAL readbacks were not responsive. Tony and I went to EX around 17:00 to verify the 20bit-DAC was installed and connected correctly, it was.

This DAC has a special AI Chassis, D1101785 "aLIGO 18 Bit AI Chassis" which has handy BNC pickoffs for all 8 channels. We put a scope on the two channels being driven by h1calex (6,7) and could see no signal.

Also the last channel on the AI is loop-backed to the first ADC AA chassis with a DB9 cable, and the IOP is configured by SDF to drive the duotone from DAC0-chan7 back to ADC0-chan30. No signal is seen there either since the upgrade.

Tue Dec 02 10:01:28 2025 INFO: Fill completed in 1min 27secs

Does not look like a good fill. Will try again tomorrow

TITLE: 12/03 Day Shift: 1530-0030 UTC (0730-1630 PST), all times posted in UTC
STATE of H1: Planned Engineering
OUTGOING OPERATOR: None
CURRENT ENVIRONMENT:
    SEI_ENV state: CALM
    Wind: 5mph Gusts, 3mph 3min avg
    Primary useism: 0.02 μm/s
    Secondary useism: 0.27 μm/s 
QUICK SUMMARY:

H1 was IDLE overnight (had troubles getting through DRMI and a few steps beyond yesterday afternoon/eve---see Oli's log).  In the middle of an Initial Alignment.  Then we'll see about locking...

Day #2 of Crane Inspection work continues:  This morning will be work for the South Bay crane, but will also need pendant work; this should go until about noon.  (Then remaining cranes would be:  Filter Cavity End Station, Staging Bldg, and some gantry cranes.)  Yesterday, rest of LVEA cranes were inspected as well as End & Mid Stations.

(it's been almost 15min and Green Arms are almost aligned from Initial Alignment.)

The IFO has been trying to relock for a bit now, but we were having multiple locklosses, from DHARD_WFSx3, BS_STAGE2, and CARM_OFFSET_REDUCTION. Most of the locklosses looked sudden (based on quick look at buildups ndscope), but the last attempt, we started getting SRM saturations and the PR gain was moving all over the place. I remembered that Jenne and RyanS had been saying that SRC1 wasn't being cooperative yesterday (88298), so I turned off the SRC1 and SRC2 loops and that stopped the oscillation. Unfortunately, we lost lock soon after in DHARD_WFS. I was (am) about to go home so I've put the detector in IDLE for the night.

h1pemex was upgraded from an 18-bit to a 20-bit DAC today, so we needed to make sure we had a calibration correction. The new filter banks that Jeff had put in (88321) for the calibration correction are called H1:PEMEX_EX_DACOUTF_1, H1:PEMEX_EX_DACOUTF_2, H1:PEMEX_EX_DACOUTF_3, and H1:PEMEX_EX_DACOUTF_4. I installed a filter called 20BitDAC that was a gain(4) in FM10 of each of these filter banks, loaded them in, and turned them on along with the input/output/gain of the filter banks. I've accepted these changes in sdf safe

Similar to what Ryan C did (88311), I've updated the saturation threshold values for ETMX M0/L1/L2/L3 and TMSX M1 stages to align with the new 28-bit DACs. Changes have been comitted to svn as r34061

I've installed a Welch WOB-L 2546B-01 at each end station to replace the Gast 523 pumps that we have been using. I've set the pressure to -19inHg and checked the flow at the dust monitor on the floor was 2.8L/min. The new pumps are much quieter, ~84dB vs ~67dB, but at a lower frequency. I'll post more photos of the setup and more details tomorrow after we see how they run over night.

Following the Beckhoff updates today (see alog88317), several settings needed to be restored in CS_ISC, EX_AUX, and EY_AUX after the initial SDF wrangling that was done after all the upgrades were finished.

As a reminder (for myself and others), when a Beckhoff computer is restarted, its settings are brought back up according to an internal settings file on that computer, NOT according to the safe.snap SDF table, unlike a traditional frontend model. This means the SDF tables for the restarted Beckhoff computers (basically anything with SYS in the name) will show several differences, that in most cases should be REVERTED. It's also useful to check the not monitored channels for differences, as we found a few of those today, although they were mostly just picomotor settings. See attached screenshots.

Tuesday Maintenance day impact notes.

Due to Beckhoff upgrades and restarts the PCAL lasers were shutoff.
When Beckhoff came back up the PCAL Lasers oddly didn't come back up this time.
The H1:CAL-PCALX_LASERPOWERCONTROL voltage was set to 0. I took that back to 5V for both arms.
Turned H1:CAL-PCALX_LASERENABLE back on. 
H1:CAL-PCALX_SHUTTERPOWERENABLE back on.

Arm specific Settings : 

PCALX: 
H1:CAL-PCALX_OPTICALFOLLOWERSERVOOFFSET was set back to 3.65V. 
H1:CAL-PCALX_OPTICALFOLLOWERSERVOGAIN : 39.60 dB

PCALY: 
H1:CAL-PCALY_OPTICALFOLLOWERSERVOOFFSET : 3.80 V
H1:CAL-PCALY_OPTICALFOLLOWERSERVOGAIN : 38.56 V

Hey future Tony,  Today is the day the X Arm 18bit DAC was changed out for a 20bit as well.