Relay Tube Removed to Install Viewport Assembly

(Jordan, Travis, Gerardo)

The relay tube connecting HAM5 and HAM7 was removed.  We had a few snags while removing it, for some reason the space between bellows is tight, perhaps due to the difference between pressure states, one chamber is under vacuum the other is not.

After the tube was out, the viewport was installed on a short assembly, the viewport and the entire assembly was leak checked and no leaks were found.  He background a the leak detector remained at 1.0x10^-10 torr*l/sec during the leak testing.

System is currently being pumped down via a small turbo plus an aux cart.

Tue CP1 Fill

Mon Dec 15 10:07:40 2025 INFO: Fill completed in 7min 37secs

 

h1sush12 IO Chassis Details

Some more details on the build of h1sush12 IO Chassis Mon 15Dec2025.

Card layout:

Adnaco Slot	Card	Interface	Notes
A1-1	Timing Card	None	Firmware upgraded in place
A1-2	empty
A1-3	ADC0 [100723-09]	NA	Original h2a ADC0, not changed
A1-4	LIGO-DAC0 [S2500460]	[S2500449]	Tested in x7sush12
A2-1	ADC1 [170619-23]	NA	Original h2a ADC1, not changed
A2-2	LIGO-DAC1 [S2500461]	[SN001]	Tested in x7sush12
A2-3	LIGO-DAC2 [S2500450]	[SN002]	Tested in x7sush12
A2-4	ADC2 [110201-08]	[S1102351]	ADC+ribbon+IF were ADC0 in h2b
A3-1	ADC3 [230509-54]	[S1102574]	ADC+ribbon+IF are new, were tested in x7sush12
A3-2	empty
A3-3	empty
A3-4	empty
A4-1	BIO0	None	Original h2a BIO0, not changed
A4-2	BIO1	None	Original h2a BIO1, not changed
A4-3	BIO2	None	Original h2a BIO2, not changed
A4-4	empty

h1sush2a's IO Chassis was rebuilt to be h1sush12.

The original ADC0, ADC1, BIO0, BIO1 and BIO2 cards were left in place, including the ADC ribbon cables and interface cards. The BIO field cables had enough slack that they did not need to be disconnected to pull the chassis out from the rack. All the other field cabling was disconnected for the upgrade.

The 7 18bit-DAC cards were removed, along with their ribbon cables and interface cards.

The one ADC from h1sush2b was removed from its chassis and installed as ADC2 (inc. ribbon and IF).

A new ADC was installed for the 4th ADC (JAC), it had been tested in x7sush12.

Following the hardware upgrade we remembered that the LIGO Timing Card needed a Firmware upgrade to run the LIGO-DACs. Marc upgraded h1sush12 Timing Card inplace using the JTAG port connected to his laptop. While he was there, he also upgraded h1susauxh2's Timing Card.

List of the 7 18bit-DACs removed from h1sush2a (in their bus order, DAC0-DAC7):

101208-06

110425-16

110425-13

110425-24

110425-17

101208-38

101208-72

h1sush2b's 2 18bit-DACs and 16bit-DAC were left in place and the chassis remains powered down, as does the MSR computer.

h1susim, h1susham1 new models restarted, DAQ restart

Jeff, Oli, Jonathan, Erik, EJ, Dave:

A new h1susim model was installed at 10:18. Some BIO slow channels were removed and a DAQ restart was required.

Later at 11:52 a new h1susham1 model was installed to correct some ADC bus selectors. No DAQ restart was required at this time.

DAQ Restart:

DAQ was restarted for h1susim model change, and we took the opportunity to add in an EDC restart to remove h1sus[h2a,h2b] channels and add corresponding h12 channels.

New H1EPICS_[FEC,SDF,CDSMON].ini files were regenerated.

OPS Midshift Report

IFO is IDLE in ENGINEERING

The LVEA has just been transitioned to LASER HAZARD following the venting of the Relay Tube.

Vent work continues with the following progress:

• LVEA Laser Hazard Transition - DONE
• HAM1 - Set irises on table to capture PSL beam pointing - ONGOING
• HAM1 - Go into PSL and add lenses -AFTERNOON
• HAM7 - Start deinstall relay tube, install viewport adapter on HAM5 side - AFTERNOON
• HAM7 - In-chamber OPO work continued - AFTERNOON
• HAM1 - Load in/stage all JAC hardware, plug in JM1 and JM3 to start testing controls - AFTERNOON
• HAM1 - Install periscopes - ONGOING
• BSC2 - FARO work - ONGOING

Other:

• DAQ Restart 10:18 PT to 10:57 PT
• There is a vacuum pump running near HAM7 reni
• Craning work in north bay LVEA
• Jeff and Oli working on SUS models

Ryan S will take over ops shift for the next few hours.

SUS RM1, RM2, and PM1 Online and Running post sush2a and sush2b merge to sush12

J. Kissel, O. Patane

After sorting the ADC readout issue (LHO:88550), the existing HAM1 HAM tip tilt suspensions (HTTS), RM1, RM2, and RM1 are now functional, damped, and aligned. They're running on the newly merged sush12 computer / IO chassis and following the drawing D0902810-v12. See analog changes in LHO:88519 and software changes in LHO:88527.

The only "interesting" thing is that these SUS used to run on a 16-bit DAC, and thus it's the first suspensions whose DACs have been upgraded that were never 18- or 20- bit DACs, as has been true of all other upgraded suspensions to-date. 
Thus there is a design choice here: for all originally 18-bit DAC suspensions, we've been putting a compensating gain in the COILOUTF banks' FM10 so tht no upstream loop that drives the suspension stage needed to account for the factor of 2^20 / 2^18 = 2^4 = 4x or 2^28 / 2^18 = 2^10 = 1024x change in gain calibration, with the filter bank named after the DAC, e.g. "20BitDAC" or "28BitDAC," respectively. For these suspensions, the "the loop won't see a difference gain" would therefore be 2^28 / 2^16 = (2^28/2^18) * (2^18/2^16) = (1024x) * (4x) = 4096x change.

For these suspensions, we could either put this factor of 4x 
   (1) In the "28BitDAC" filter bank in FM10, and have the *value* of that bank be different for these suspensions (4096x) vs. other suspensions (1024x).
   (2) Make the "28BitDAC" filter bank in FM10 the same (the factor of 1024x), and compensate the loops further upstream.

Today, we chose (2).

That leaves four places to compensate:
    (a) DAMP the local damping loops
    (b) TEST the test banks from which we usually drive the "health check" transfer functions.
    (c) OPTICALIGN the banks from which we drive alignment offsets
    (d) LOCK the filter banks that receive and alter the ASC centering loops as necessary.

We've chosen to install the factor of 4x within the gain_{L,P,Y} FM4 filters for (a) [see filter file changes]. For all other banks, I've installed the factor of 4x directly in the EPICs gain field [see SDF file changes].

That means all existing SUS in HAM1 are fully functional on the newly merged sush12 computer / IO chassis and following the drawing D0902810-v12. See analog changes in LHO:88519 and software changes in LHO:88527.

NEW! JM1, JM3, and JM ALL SUS medm screens, plus updated RM ALL screen (+ macro file updates)

I've created macro files for JM1, JM3, and JM ALL, and there are new SUS medm screens in the sitemap in the dropdown that was previously named IM/RM/PM but is now named HAM12 HSSS. In the process of making the JM ALL screen, I also made the RM ALL screen more generic so it can be more easily copied in the future. Also also, the macro files for RM1, RM2, RM ALL, and RM1 have all been updated to have the correct readouts the correspond to the DAC upgrades. All these changes have been committed to the svn

Macro files: userapps/sus/common/medm/sus{jm1,jm3,jmall,rm1,rm2,rmall,pm1}_overview_macro.txt r34219

JM ALL, RM ALL medm screens: userapps/sus/common/medm/hsss/SUS_CUST_{JM,RM}_OVERVIEW_ALL.adl r34218

Sitemap: userapps/cds/h1/medm/SITEMAP.adl r34220

Recovery of RMs and PM1s exposed ADC Channel Issues; Front-end Code Model Prep for Fix

J. Kissel, O. Patane, D. Barker

Oli and I have moved on to recovering the SUS RM1, RM2, and PM1 post their migration from the h1sush2b computer / h1sushtts front-end model into the newly merged h1sush12 computer / IO chassis system and h1susham1 front-end model yesterday (see LHO aLOGs 88519 and 88527). We immediately noticed that all the raw OSEM ADC inputs were digital 0. We opened up the ADC MONITOR screen and found this auto-generated screen completely blank. Popped open the IOP for the whole computer to check it's report of these ADC cards, and they appeared normal. See attached MEDM screen collection.

Dave and I opened up the new h1susham1 front-end model and found that the bus selectors that were parsing the ADC2_2_HTTS and ADC3_2_HTTS goto tags were configured to read the Direct I/O Chassis ADC blocks' internal bus creator / output name rather than the card number. It's easier shown than described -- check out the before (r34117) vs. after (r34217) top level model.

I fixed this as one usually does -- 
    - double clicking on the bus selector, 
    - highlighting the channels from the "Signals on the bus" list that you want (which say, e.g. "adc_0_16, adc_0_17, adc_0_18, adc_0_19" instead of "adc_2_16, adc_2_17, adc_2_18, adc_2_19"), 
    - hitting "Select >>," to bring them over to the "Selected Signals," then 
    - deleting any "Selected Signals" which have question marks in front of them (i.e. "??adc_2_16").

This needed doing for all ADC2 and ADC3 bus selectors fed into the RM1, RM2, PM1, JM1, and JM3 library blocks, with channels selected so they match the along AA chassis input for those cards from D0902810-v12.

The new top level model has been committed to userapps svn rev r34217.

D. Barker, J. Kissel, O. Patane 

This h1susham1 front-end model change has been installed as of 2025-12-18 19:55 UTC. Dave will likely post an official aLOG eventually.
All signs point toward "success!"

Old OPO inspection after the swap from HAM7

[Eric, Daniel, Karmeng]

We transferred the OPO from LVEA to optics lab, uncovered the lids and everything looks good.

Touch the mirror mounts and mirrors, no failure except for M3, which swivels off the mount, only part of the glue holding the mirror on the mount.

TSC Chiller top off

FAMIS 27830 TCS Chiller top off

12/16/2025    Tony    30.7    100    30.8    10.2    125    10.4    Top of ball reading

SUS IM1, IM2, IM3 and IM4 Online and Running post sush2a and sush2b merge to sush12

J. Kissel, O. Patane

After having sorted issues with the (non-existent) binary IO (see LHO:88542 and LHO:88544), and Oli has performed all the "usual" controls updates after a 32CH DAC upgrade, all of the HAUX suspensions -- IM1, IM2, IM3, IM4 -- are now confirmed functional, damped, and aligned.

We've left their guardians them in the ALIGNED state.

That means all SUS in HAM2 are fully functional on the new merged sush12 computer / IO chassis and following the drawing D0902810-v12. See analog changes in LHO:88519 and software changes in LHO:88527.

Update to SUSIM Binary IO MEDM Overview -- Stripping it of Old Fully Functional BIO Infrastructure; Replacing with Reality of Jumpered Switches

J. Kissel

The issues we found with the IM's binary IO motivated me to update the MEDM screen interface to the system -- namely making it more like other HAM Single Stage Suspensions (HSSS) and the top masses of HAM X Double Suspensions (HPDS, HDDS, HTDS, HSDS) which clearly indicate that the HAM-A drivers they use have had their remote binary IO control / readbacks disabled.

At LHO the MEDM screens that call the interface are
    /opt/rtcds/userapps/release/sus/common/medm/haux/
        SUS_CUST_HAUX_MONITOR_OVERVIEW_all.adl
and
    /opt/rtcds/userapps/release/sus/common/medm/hsss
        SUS_CUST_HSSS_OVERVIEW.adl

which now *both* call the same BIO screen, which I've moved
    FROM
    /opt/rtcds/userapps/release/sus/common/medm/
        haux/SUS_CUST_HAUX_BIO_ALL.adl

    TO
        hsss/SUS_CUST_HAUX_BIO_ALL.adl 
then modified and committed the svn location change. See BEFORE and AFTER.

I then edited the following macros to change the SUSTYPE or sustype variables from "IM" or "im" to "HAUX" or "haux."

    /opt/rtcds/userapps/release/sus/common/medm/
        susim1_overview_macro.txt
        susim2_overview_macro.txt
        susim3_overview_macro.txt
        susim4_overview_macro.txt
        susimall_overview_macro.txt
These have *not* been committed to the svn as the macros also contain all of the ADC / DAC / AI / AA / front-end configurations that have diverged for suspensions at L1 and H1. 

Some very late medm screen change commits

It turns out I never committed some medm SUS overview screens to svn after we removed the USER DACKILL back a long time ago, so I just committed them. They are /userapps/sus/common/medm/:

• haux/SUS_CUST_HAUX_OVERVIEW.adl r34206
• opos/SUS_CUST_OPOS_OVERVIEW.adl r34208
• hxds/SUS_CUST_HTDS_OVERVIEW.adl r34211
• omcs/SUS_CUST_OMCS_OVERVIEW.adl r34214

Recovery of IMs exposed double-usage of MC1 and MC3 Binary IO Cards by IMs; Front-end Code Model Prep for Fix

J. Kissel, O. Patane,

Oli and I have moved on to recovering the SUS IMs post their migration from the h1sush2b computer into the newly merged h1sush12 computer / IO chassis system yesterday (see 88519 and 88527), but immediately noticed that the MEDM OVERVIEW screen reported that the test/coil enable bits were in apparently non-functional state (see "before" OVERVIEW and BIO screens).

Thinking through it, and remembering that the IM's binary IO switching had been rendered "defunct" back in July 2022 during their upgrade of HAM-A coil drivers (LHO:64171 manifesting ECRs E2200307, E2400048, and E2500295), we release that the digital representations of the sush2b BIO card read/write had never been removed from the h1susim model. Prior to the sush2b + sush2a = sush12 merge, talking to the sush2b card didn't matter. 

But now that this model is running on the merged chassis, the digital representation of talking to binary card 0 and card 1 means that that both the h1susmc1 and h1susim models are talking to the same BIO card (card 0 and card 1, the lower an upper halves of the physical BIO0 card) in the sush12 chassis! No bueno.

This double comms is confirmed by comparing the top level and BINARY DECODE block of h1susmc1 (userapps svn rev r33947) model's Binary IO communications to the "before" communications within the h1susim model top level (userapps rev r33974).

As such, I've modified the top level of the h1susim model to remove all digital representation of the cards, and sending 85 = 01010101 ("the Test/Coil switch is set to COIL enabling drive from the DAC, and the LP is ON" for each of the 4x suspensions) into the EPICs readback to indicate / match reality, and terminating the top level control request. See top level of the model now committed as rev r34204.

D. Barker, E. von Ries, J. Kissel

This h1susim front-end model change has been installed as of 2025-12-18 18:25 UTC. Dave will likely post an official aLOG eventually.
All signs point toward "success!"

SUS MC1, MC3, PRM, and PR3 Online and Running post sush2a and sush2b merge to sush12

J. Kissel, O. Patane

We've recovered all damping and alignment functionality for H1SUSMC1, H1SUSMC3, H1SUSPRM, and H1SUSPR3  (including turning on L, P. and Y Estimators for PR3); the HAM {Small, Large} Triple Suspensions (HXTS, HSTS, HLTS) on HAM2 after their host computer changed from h1sush2a to h1sush12 and their DACs were upgraded to a 32CH 28-bit LIGO DAC (see analog changes in LHO:88519 and software changes in LHO:88527).

The recovery was relatively simple for these suspensions:
- Untripped the software watchdogs for these HAM2 suspensions (H1:IOP-SUS_MC1_DACKILL_RESET, H1:IOP-SUS_MC3_DACKILL_RESET, H1:IOP-SUS_PRM_DACKILL_RESET, H1:IOP-SUS_PR3_DACKILL_RESET) and the HAM2 seismic system beneath it (H1:IOP-SEI_HAM2_DACKILL_RESET).
- Used SEI_HAM2 guardian to bring HAM2 SEI system to ISI_DAMPED_HEPI_OFFLINE (from them having had their watchdogs trip overnight).
- Left / made sure that SUS Guardians in SAFE and unmanaged
- Added a gain of 2^10 = 1024x in the COILOUTF banks in FM10 to compensate for the 18-bit DAC to 28-bit 
- Turned off inputs to the COILOUTF, untripped watchdogs, turned MASTER SWITCH ON
- Added small 5 count offsets in COILOUTF, one-at-a-time, and sorted out the MEDM overview macro files***
    - lower masses needed adjusted due to the consolidation of DACs
    - Computer name changed from h1sush2a to h1sush12
- Tested functionality of binary IO by switching H1:SUS-{MC1,MC3,PRM,PR3}_BIO_{M1,M2,M3}_STATEREQ into various states confirming that the read backs switch correctly (and at this point, we just assume that the binary OUT is actually switching the coil drivers).
- With the SUS guardian still in SAFE, and the MASTER SWITCH still ON, and watching the top mass OSEMs on ndscope ^^^, 
    - Turned on damping loops one DOF at a time, to confirm that resonant motion exponentially decays as expected without any saturation (reminding ourselves that the DAC saturation limit is now +/-2^27 = +/- 134217728 [DAC ct]_{peak})
    - Turned on alignment offsets to see a significant shift in top mass
- Seeing no issue, used the SUS guardian to bring the suspension to ALIGNED, then back to SAFE, then back to ALIGNED.

*** The MEDM overview macro files are 
    /opt/rtcds/userapps/release/sus/common/medm/
        susmc1_overview_macro.txt
        susmc3_overview_macro.txt
        susprm_overview_macro.txt
        suspr3_overview_macro.txt

^^^ Handy ndscope command line to quickly switch between 'scopes of the top mass EULER basis report of OSEM motion
    $ optic=MC1;ndscope -k H1:SUS-${optic}_M1_DAMP_{L,P,Y}_IN1_DQ &

CDS Upgrade Summary: Monday 15th December 2025

Merge h1sush2a/2b to form h1sush12

Jeff, Oli, Fil, Marc, Erik, Jonathan, EJ, Dave

h1sush2a was upgraded to become h1sush12, with h1sush2b being powered down for now.

In the MSR, the supermicro W2245 h1sush2a was removed from the rack and in its place the new W3323 h1sush12 was installed. The IX Dolphin card and cable was transferred to the new machine.

In the CER H1SUSH2A IO Chassis was upgraded to become H1SUSH12:

The ADC was removed from sush2b to become the third ADC in sush12.

All the 18bit DACs were removed.

3 LIGO-DACs were installed, along with a new 4th ADC.

The 3 Binary cards were left in place. In fact their cables were long enough to remain attached while the chassis was pulled out from the rack.

New models for h1iopsush12, h1sus[mc1,mc3,prm,pr3,im,ham1] were added. Note that h1sushtts is now called h1susham1. A DAQ restart was needed.

More details will follow.

New ASCIMC, LSC models

Jennie, Dave:

New h1ascimc and h1lsc models were installed. A DAQ restart was needed.

Beckhoff changes

Daniel, Dave:

Daniel installed new CS-ISC beckhoff PLC. A DAQ restart was needed.

DAQ Restart

Dave, Jonathan.

The DAQ was restarted for:

retire iopsush2a, iopsush2b. Add new iopsush12

h1sush12 user model changes

new h1ascimc and h1lsc models

EDC restart for ECAT CS ISC.

RF distribution for JAC

A 5 dB attenuator was added at the input of the RF doubler for the JAC 43 MHz generation. This brought the input level to a nominal 10 dBm. 

SUS-C3 and SUS-C4 AI Chassis Upgrades Complete; Merged sush12 ADC/DAC to AA/AI Chassis Cabling Installed

F. Clara, J. Figueroa, J. Kissel, M. Pirello
ECR E2400409 and E2500296 (IIET 35739 and 35706, respectively)
WP 12901
DWG D0902810-v12
DCN E2500341

Today we've gone forward with merging the sush2a and sush2b IO chassis, facilitated by upgrading those SUS's DAC cards to 32 CH, 28- bit DACs (D2200368). This entry covers the analog electronics and cabling that were impacted by the change, covering that all of the suspensions in, or soon to be in HAM1 and HAM2 -- MC1, MC3, PRM, PR3, IM1, IM2, IM3, IM4, RM1, RM2, PM1, JM1, and JM3.

We followed changes outlined in E2500341 which highlights the changes in the sush12 SUS electronics system drawing from D0902810-v11 to D0902810-v12. 
That required 
    - disconnecting all affected AI output cables in SUS-C3 and SUS-C4,
    - Removing the existing 6x 2x 8CH DAC AI chassis (D1000305), 
    - modifying them to become D2500353 1x 32CH AI chassis 
        . replacing the 2x 8CH AI rear panel with WD relays (D1000551) with 1x 32CH AI rear panel without WD relays (D2500097)
        . replacing the 2x 8CH back panel (https://dcc.ligo.org/LIGO-D1000552 with 1x 32CH back panel (D2400308)
    - re-installing, then
    - cabling everything up according to the D0902810-v12 version of the wiring diagram.

Here's the list of modified AI chassis serial numbers and assignment:
                                                     D1000305 > D2500353     D2500097
SUS Chain                     Rack / Position        Chassis S/N             Rear Board S/N          32CH DAC Card / IO Slot      Channels (Counting from 0)
MC1, MC3, PRM TOPs            SUS-C4 / U30           S1104370                S2501311                DAC0 / #2                     0-15
PRM, PR3 TOPs MC1 MID BOT     SUS-C4 / U29           S1104374                S2501315                DAC0 / #2                    16-31

MC3, PRM MID/BOT              SUS-C4 / U22           S1104375                S2501310                DAC1 / #4                     0-15
PR3 MID/BOT, RM1, RM2         SUS-C4 / U21           S1104378                S2501312                DAC1 / #4                    16-31

IM1, IM2, IM3, IM4            SUS-C4 / U10           S1104377                S2501314                DAC2 / #5                     0-15
PM1, JM1, and JM3             SUS-C4 /  U2           S1102760**              S2501313                DAC2 / #5                    16-31

** Technically, the (now) PM1, JM1, and JM3 AI chassis S1102760 was a 16-bit DAC AI chassis (D1101521) instead of a D1000305 at the start of today, and it didn't *need* the additional 16CH pass-through SCSI connection, but in the spirit of making everything the same, we elected to make it a full "new normal" D2500353 chassis.

Pictures of the now-D2500353 AI chassis rear boards and their connections. They're attached in the order of rear board serial numbers; the corresponding chassis number is listed above.